Experience : 3+ Years

nNotice Period : Immediate to 30 days.

nJob Description:

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- Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus)
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- Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure
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- Work closely with design team to come up with preplacement requirements & timing constraints
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- Work closely with physical design team for floorplan, placement & timing reviews
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- Work closely with cross-functional teams to review standard cell profile, timing models & memory models
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nSkills:

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- Positive understanding of ASIC design flow
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- Hands on experience in synthesis and static timing analysis
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- Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must
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nExperience in Perl, TCL and shell scripting is desirable

n* Excellent interpersonal & analytical skills with ability to work independently

nBachelors or Master's Degree with a strong VLSI Background

📌 Synthesis Engineer (Bengaluru)
🏢 Mirafra Technologies
📍 Bengaluru