Hi, /n /n Good Day to you! /n /n :: /n /n

- ASIC/SoC Design position is your chance to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture.

/n /n /n Skills: /n Microarchitecture, PCIe, USB, Ethernet, DDR3/4, LPDDR, AXI, I2C/I3C, SPI, SD/SDIO/eMMC, UART, PTPX, Optimisation, 2/3/4/5/6nm nodes. /n /n We are looking for candidates with 7–20 years of experience who can join with us and part of ODC long term project. /n /n Roles & Responsible:: /n /n

- Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, design functional blocks using System Verilog RTL code, and conduct synthesis and route to meet timing / area goals

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- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)

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- Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts

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- Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)

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- Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team

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- You handle Verilog RTL logic design and debug

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- Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation

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- Contribute as a design engineer developing the next-generation of multi-core processors

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- Specify, design, and synthesize RTL blocks, optimize and floorplan them

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- Work with verification engineers to ensure accuracy.

/n /n /n Thanks, /n P Mohankrishna, /n [email protected]

📌 Senior Design Engineer (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru