LEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIA /n Location: Hyderabad / Pune / Chennai (India) /n /n JOB SUMMARY /n We are seeking a Lead Behavioral Modeling Engineer to join Lattice Semiconductor's FPGA Architecture & Design team. You will lead development of behavioral and architecture models for next-generation low-power FPGA fabrics, own power and timing characterization, and mentor a small modeling team. /n This is a technical leadership role focused on modeling methodology and design optimization—not traditional product RTL design or verification. /n /n KEY RESPONSIBILITIES /n /n

- Develop and maintain behavioral models for FPGA fabric elements (CLBs, routing, interconnects, logic blocks)

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- Own power and timing characterization across PVT (Process, Voltage, Temperature) corners

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- Build Python-based automation flows for rapid design exploration and PPA analysis

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- Lead modeling methodology improvements and drive continuous optimization

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- Collaborate with architecture, RTL, and circuit design teams to validate design intent

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- Mentor and guide modeling engineers on best practices and technical excellence

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- Correlate behavioral models against silicon measurements and real chip data

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- Establish and communicate modeling standards and documentation

/n /n /n REQUIRED QUALIFICATIONS /n /n

- Bachelor's degree in Electrical Engineering or related field (Master's preferred)

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- 8+ years in behavioral/architecture modeling or FPGA/ASIC design

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- 2+ years of technical leadership experience

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- Proficiency in C++, SystemC, and Python for model development

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- Deep knowledge of FPGA fabric architecture (CLBs, LUTs, routing, interconnects)

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- Strong understanding of power and timing characterization methodologies

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- Excellent problem-solving and technical communication skills

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- Ability to lead cross-functional teams and drive collaborative efforts

/n /n /n PREFERRED QUALIFICATIONS /n /n

- Master's degree (M.Tech, MS) in Electrical/Computer Engineering

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- Prior experience at semiconductor companies

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- Published papers or patents in FPGA modeling or architecture optimization

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- Experience with ML-based power prediction or on-die sensor integration

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- Test-chip bring-up and silicon validation experience

/n /n /n WHAT YOU WILL NOT BE DOING /n This role is NOT focused on: /n /n

- Verilog/VHDL/SystemVerilog code development for product design

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- SystemVerilog testbench and formal verification

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- Gate-level or post-layout simulation

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- Traditional Design Verification (DV)

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- Physical design (place & route, floorplanning)

/n /n /n If your background is primarily RTL design or DV, this may not be the right fit. /n /n WHY LATTICE SEMICONDUCTOR? /n Lattice is the global leader in low-power FPGA solutions for edge AI, automotive, aerospace, and IoT. Your modeling work directly impacts next-generation FPGA architectures and time-to-market for innovative products. /n /n We offer: /n /n

- Deep technical challenge and leadership opportunity

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- Cooperative, innovation-driven culture

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- High-impact products used globally

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- Competitive compensation and benefits

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📌 LEAD BEHAVIORAL MODELING ENGINEER - LATTICE SEMICONDUCTOR INDIA (Hyderabad)
🏢 Lattice Semiconductor
📍 Hyderabad