Designation- ASIC Principal Design Engineer /n Exp-10+ yrs /n Location- Bangalore /n /n JD- /n Responsibilities: /n /n

- Define and architect high-performance blocks for the latest, most advanced networking ASICs

/n

- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power

/n

- Collaborate with the verification team in the development of the testplan and assist in debugging test failures

/n

- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

/n /n /n Required Skills: /n /n

- Strong Verilog RTL coding skills

/n

- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable

/n

- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus

/n

- Knowledge of high performance memory subsystems

/n

- Knowledge of multi-domain clock synchronization and high-speed serial interfaces

/n

- Robust problem solving and ASIC debugging skills

/n

- Excellent written and verbal communications skills

/n

- MSEE or BSEE is required with 8 plus years of experience

/n /n

📌 ASIC Principal Design Engineer (Bengaluru)
🏢 Macrohire
📍 Bengaluru