ASIC/SOC Front End Design Engineer : 1. Setup ASIC QA flows for RTL design quality checks. 2.

Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3.

Running

Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.

- Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
- Checking the flow errors, design errors & violations and reviewing the reports.
- Debugging CDC, RDC issues and come up with the RTL fixes.
- Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
- Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
- Flows or Design porting to different technology libraries.




- Generating RAMs based on targeted memory compilers and integrating with the RTL.
- Running functional verification simulations as needed.

Job Requirements: 1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience 2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes 3. Contemporary SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation 4.

Experience in signoff of front end quality checks & metrics for various milestones of the project 5. TCL, Perl, Python scripting Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate

📌 Application Specific Integrated Circuit Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad