Job Description

Senior Analog Layout Engineer

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Location: Hyderabad

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Experience: 4–10 Years

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Role Overview

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We are looking for a Senior Analog Layout Engineer with strong hands-on experience in advanced-node custom/analog layout, particularly 2nm, 3nm, and 5nm FinFET technologies.

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Key Responsibilities

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- Own block-level analog/custom layout from floorplanning to tapeout.
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- Develop layouts for analog, mixed-signal and custom circuit blocks.
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- Work on advanced-node technologies including 2nm/3nm/5nm FinFET.
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- Apply matching, symmetry, common-centroid, shielding and sensitive-net routing techniques.
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- Optimize layouts for parasitics, PPA, EM/IR and signal integrity.
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- Perform and debug DRC, LVS, ERC and PEX.
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- Analyze layout-dependent effects (LDE) and minimize post-layout performance impact.
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- Collaborate closely with Analog Design, Circuit Design and Physical Verification teams.
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Core Technical Skills

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- 4–10 years of relevant Analog/Custom Layout experience.
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- Strong hands-on experience with Cadence Virtuoso / Custom Layout.
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- Proven experience in 2nm / 3nm / 5nm FinFET technologies.
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- Solid understanding of advanced-node design rules and device layout.
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- Expertise in matching, common-centroid, shielding, guard rings and isolation.
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- Experience with Calibre/PVS, DRC/LVS/ERC and PEX.
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- Strong understanding of parasitic extraction and post-layout analysis.
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- Tapeout experience in advanced technology nodes is highly preferred.
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Ideal Profile

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A hands-on analog layout engineer capable of delivering tapeout-quality custom layouts at advanced FinFET nodes, with strong ownership of layout quality, parasitic optimization and physical verification.

📌 Senior Analog Layout Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad