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- Define and architect high-performance blocks for the latest, most advanced networking ASICs
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- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
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- Collaborate with the verification team in the development of the testplan and assist in debugging test failures
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- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
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Required Skills:
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- Robust Verilog RTL coding skills
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- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
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- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
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- Knowledge of high performance memory subsystems
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- Knowledge of multi-domain clock synchronization and high-speed serial interfaces
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- Strong problem solving and ASIC debugging skills
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- Excellent written and verbal communications skills
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- MSEE or BSEE is required with 8 plus years of experience
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📌 ASIC Principal Design Engineer (Bengaluru)
🏢 Macrohire
📍 Bengaluru
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