Lead Design Verification Engineer

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are looking for a Lead Design Verification Engineer with robust hands-on expertise in DDR5 / LPDDR5 verification to drive verification of high-performance memory interfaces and controllers.

Key Responsibilities
Own verification planning, environment development, execution, and signoff for DDR5/LPDDR5 IPs.
Develop and enhance SystemVerilog/UVM verification environments.
Verify DDR5/LPDDR5 protocol, controller functionality, initialization, training, timing, and error scenarios .
Develop UVM sequences, monitors, scoreboards, checkers, assertions, and functional coverage .
Drive constrained-random, directed, stress, and corner-case testing .
Debug complex RTL, protocol, timing, and simulation failures .
Drive coverage closure, regression infrastructure, and verification signoff .
Collaborate with RTL, architecture, firmware, PHY, and system validation teams .




Mentor engineers and drive verification methodology improvements.

Core Technical Skills
6–10 years of Design Verification experience.
Strong hands-on expertise in DDR5 / LPDDR5 verification.
Expert knowledge of SystemVerilog, UVM, SVA, and functional coverage .
Strong understanding of DDR protocols, memory controller architecture, initialization and training flows .
Experience with timing, calibration, power-management, error handling, and corner-case scenarios .
Robust debug and root-cause analysis skills.
Proficiency in Python/Perl/Tcl for verification automation.
Experience with DDR PHY verification, VIP, emulation, or FPGA prototyping is a plus.

Ideal Profile: A hands-on verification lead who can drive DDR5/LPDDR5 verification from strategy and UVM development through coverage closure and signoff , while providing robust technical leadership to the team.

📌 Lead Design Verification Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru