14 Sep
|
Important Group
|
Bengaluru
14 Sep
Important Group
Bengaluru
Have good knowledge of entire physical design process from floorplan till GDS generation
* Good Exposure to Physical Verification Process
* Have hands -on experience in latest sub -micron technologies below 10 nm
* Hands -on experience in leading PnR tools Synopsys ICC/ICC2
* Experience in low power designs and handling congestion or timing critical tiles will be preferred
* Should be a quick learner and have good attention to detail
* Experience in ECO implementation preferred
* Scripting skills in Perl/Tcl/Python etc
* Must have good communication & problem -solving skills.
* Should be able to handle PnR tasks with minimal supervision
Requirements
BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
Hands -on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
Robust experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
Experience with back -end design tools such as Primetime, Innovus, RedHawk, etc.