Job DescriptionQualification: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI or related disciplines

NWhat You'll Be Working On:

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Block-level and full-chip Static Timing Analysis
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Development, validationand debugging of SDC constraints
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Setup, Hold, Recovery &Removal; analysis
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MCMM timing analysis across PVT corners
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Timing closure across multiple design scenarios
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Root-cause analysis andresolution of timing violations
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Clock timing and clock architecture analysis
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Timing ECOs and implementation changes
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Timing sign-off and generation/review of timing reports
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OCV / AOCV / POCV and derating analysis
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Signal Integrity / Crosstalk-aware timing analysis
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Timing closure for high-performance and complex SoC/ASIC designs
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nWhat We're LookingFor

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6+ years of hands-on STA experience
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Solid expertise in Synopsys PrimeTime and/or Cadence Tempus
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Excellent understandingof STA concepts and timing methodologies
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Robust experience with SDC constraints
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Valuable understanding of MCMM, OCV, AOCV & POCV
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Strong knowledge of clock architecture, clock timing and clock-related issues
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Experience with timing ECOs and timing closure methodologies
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Good understanding of the ASIC Physical Design flow
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Robust Tcl scripting skills
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Python scripting knowledge will be an added advantage
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nGood to Have

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Full-chip STA and sign-off experience
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Experience with advanced technology nodes
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Exposure to Signal Integrity / Crosstalk analysis
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Experience with low-power designs
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Experience working on large and complex SoC designs
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📌 Sta Lead Karnataka
🏢 Leadic Design
📍 Karnataka