This role is for one of Weekday’s clients

Min Experience: 4+ years
Location: Hyderabad, Bengaluru, Karnataka, India
JobType: full time

We are looking for a skilled and experienced DFT Engineer with 4–12 years of experience in semiconductor design and test methodologies. The ideal candidate will have robust hands-on expertise in ATPG and Scan Insertion, with a solid understanding of DFT architecture, testability requirements, and silicon validation. Experience with MBIST will be an added advantage.

You will work closely with RTL design, physical design, verification, and product engineering teams to develop and implement robust DFT solutions for complex SoCs and ASICs. The role involves driving DFT implementation from architecture and insertion through ATPG generation, pattern validation, coverage analysis, and production readiness.

Requirements

Key Responsibilities
Develop and implement DFT architectures and methodologies for ASIC/SoC designs.
Perform scan insertion across hierarchical and full-chip designs while ensuring design integrity and testability.




Develop, configure, and debug ATPG environments for stuck-at, transition, and other applicable fault models.
Generate, validate, and optimize ATPG patterns to achieve high fault coverage and effective test application.
Analyze ATPG results, identify coverage gaps, and implement corrective measures to improve test coverage.
Work on scan chain configuration, stitching, balancing, and verification.
Debug DFT-related issues across RTL, gate-level netlists, and post-synthesis/post-layout stages.
Collaborate with RTL, synthesis, physical design, STA, verification, and validation teams to resolve DFT implementation challenges.
Review DFT constraints and ensure compatibility with synthesis and physical implementation flows.
Perform DFT rule checks, identify violations, and support their closure.
Analyze test coverage, pattern quality, test time, and compression requirements.
Support gate-level

📌 Dft Engineers Hyderabad
🏢 Weekday AI
📍 Hyderabad