Job DescriptionQualification: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI or related disciplines
NWhat You'll Be Working On:
N
n
Block-level and full-chip Static Timing Analysis N
Development, validationand debugging of SDC constraints N
Setup, Hold, Recovery &Removal; analysis N
MCMM timing analysis across PVT corners N
Timing closure across multiple design scenarios N
Root-cause analysis andresolution of timing violations N
Clock timing and clock architecture analysis N
Timing ECOs and implementation changes N
Timing sign-off and generation/review of timing reports N
OCV / AOCV / POCV and derating analysis N
Signal Integrity / Crosstalk-aware timing analysis N
Timing closure for high-performance and complex SoC/ASIC designs N

nWhat We're LookingFor
N
n
6+ years of hands-on STA experience N
Strong expertise in Synopsys PrimeTime and/or Cadence Tempus N




Excellent understandingof STA concepts and timing methodologies N
Robust experience with SDC constraints N
Positive understanding of MCMM, OCV, AOCV & POCV N
Robust knowledge of clock architecture, clock timing and clock-related issues N
Experience with timing ECOs and timing closure methodologies N
Valuable understanding of the ASIC Physical Design flow N
Strong Tcl scripting skills N
Python scripting knowledge will be an added advantage N

nGood to Have
n
N
Full-chip STA and sign-off experience N
Experience with advanced technology nodes N
Exposure to Signal Integrity / Crosstalk analysis N
Experience with low-power designs N
Experience working on large and complex SoC designs N

📌 Sta Lead Karnataka (India)
🏢 Leadic Design
📍 India