Key Responsibilities: /n /n
Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
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Participate in defining the architecture and microarchitecture features of the CPU design.
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Write RTL and optimize logic for power, performance, area, and timing goals.
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Ensure design integrity for physical implementation through effective strategies, tools, and methods.
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Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
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Document microarchitectural specifications (MAS) for the CPU features.
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Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.
/n /n /n Minimum Qualifications: /n /n
7+ years experience in RTL design using Verilog, V2K, or System Verilog, with strong knowledge of hardware modeling and logic debug environments.
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5+ years experience with contemporary energy-effective and low-power logic design methods, including techniques applicable to high-frequency optimization.
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5+ years experience in Cross-clock domain crossings and power aware design.
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3+ years experience in scripting languages such as TCL, Perl, or Python.
/n /n /n Preferred Qualifications: /n /n
Knowledge on CPU power-management namely power/electrical budgeting, energetic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
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Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
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Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
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Familiarity with circuit planning and timing convergence processes.
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Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
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Proficient with static timing analysis, UPF and lint checks.