Job DescriptionWe're Hiring | Memory Layout Engineers

NWe're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.

NExperience: 4+ Years

NLocation: Bangalore

NKey Responsibilities:

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- Design memory layouts for various building blocks, including:
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- Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
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- Integrate top-level memory layouts.
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- Perform physical verification using DRC and LVS.
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- Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
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- Analyze layouts for power integrity and signal integrity.
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- Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.
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nRequired Skills:

NStrong hands-on experience in Memory Layout for advanced technology nodes.

NExpertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).

NSolid understanding of physical verification, layout methodologies, and semiconductor design flows.

NScripting knowledge is anadded advantage.

📌 Hiring: Memory Layout Engineer (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru