ASIC RTL Design Engineer

Experience: 5–12 Years | Location: Bangalore

We are looking for an experienced ASIC RTL Design Engineer to work on complex IP, subsystem and SoC development.

Key Responsibilities:
Develop and implement RTL designs using Verilog/SystemVerilog .
Work on microarchitecture, RTL coding, integration and functional debugging .
Develop high-quality, synthesizable RTL and participate in design reviews .
Collaborate with Architecture, DV, PD, DFT and Emulation teams.
Debug design issues and support simulation, synthesis and timing closure .
Contribute to SoC/IP integration and sign-off activities .

Required Skills:
Robust experience in Verilog/SystemVerilog and RTL design .
Valuable understanding of ASIC design flow and digital design concepts .
Experience with IP/Sub-system/SoC development and integration .
Knowledge of protocols such as PCIe, DDR, AMBA/AXI is an advantage.
Robust debugging and problem-solving skills.

Education: B.E./B.Tech/M.E./M.Tech in ECE/EE/CS or related field.

📌 Asic Rtl Engineer Bangalore Metropolitan Area (India)
🏢 XQwave(Formerly Obsidian Solutions
📍 India