Job Summary /n We are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII. The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams. /n Key Responsibilities /n /n
Execute the complete physical design flow:

/n
Floorplanning

/n
Power planning

/n
Placement

/n
Clock Tree Synthesis (CTS)

/n
Routing

/n
Optimization

/n
ECO implementation

/n
Physical sign-off

/n
Perform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations.

/n
Analyze and optimize timing, power, area, congestion, and signal integrity.

/n
Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure.

/n
Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions.

/n
Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks.

/n
Debug placement, routing, congestion, timing, and physical-design violations.

/n
Collaborate with RTL, synthesis, STA, DFT, power, and verification teams to achieve project milestones.

/n




Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets.

/n
Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting.

/n
Participate in methodology development and automation initiatives.

/n /n Required Technical Skills /n /n
Robust understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII.

/n
Valuable knowledge of:

/n
Floorplanning

/n
Placement

/n
CTS

/n
Routing

/n
Timing closure

/n
ECO

/n
Physical verification

/n
Power planning

/n
Solid understanding of setup/hold timing and STA.

/n
Knowledge of MMMC analysis and timing constraints.

/n
Experience with industry-standard EDA tools such as:

/n
Cadence Innovus

/n
Synopsys ICC2/Fusion Compiler

/n
Synopsys PrimeTime

/n
Cadence Tempus

/n
Calibre/ICV

/n
Scripting knowledge in Tcl, Python, Perl, or Shell.

/n
Understanding of DRC, LVS, EM/IR and power integrity is preferred.

/n
Exposure to low-power design/UPF and advanced technology nodes is an advantage.

/n /n Education /n /n
B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related field.

/n /n Experience /n 3–6 years: Physical Design Engineer

📌 Pd Engineer Noida
🏢 Mirafra Technologies
📍 Noida