Key Responsibilities:
Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions).
Perform block level and full chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios.
Own RTL synthesis (Design Compiler/Fusion Compiler/Genus), including constraint setup, QoR optimization, and netlist quality checks.
Analyze timing violations, identify root causes, and collaborate with RTL, PD, and architecture teams to resolve issues.
Validate constraints across synthesis, PnR, and sign off stages to ensure correctness and consistency.
Drive timing ECOs and support post route optimization to achieve sign off timing.
Generate timing reports, summarize key risks, and propose optimization strategies.
Mentor junior engineers on STA, SDC, and synthesis best practices.

Required Skills & Experience:




3 - 5 years of hands on experience in STA, constraints development, and synthesis.
Solid understanding of STA fundamentals (setup/hold, OCV/AOCV/POCV, SI, derates, CPPR).
Expertise in Synopsys PrimeTime or Cadence Tempus for timing analysis.
Robust synthesis experience with Design Compiler, Fusion Compiler, or Cadence Genus.
Solid understanding of RTL to GDSII design flow and SoC timing architecture.
Robust Tcl scripting skills; Python/Perl preferred.
Proven ability to independently debug complex timing/synthesis issues and drive closure.
Excellent communication and cross functional collaboration skills.

📌 Physical Design Pd Engineer Bengaluru
🏢 Ad Astra Consultants
📍 Bengaluru