Job DescriptionLocation: Noida, Bangalore & Hyderabad
nExperience: 2-8 years
nAvailability: Immediate Joiners Only
nJob Description
nWe are seeking a solid Digital Physical Design Engineer to drive block-level physical implementation of complex SoCs/ASICs across advanced nodes.
nThe role involves hands-on execution and ownership of key blocks from synthesis to tape-out, ensuring closure across timing, power, area, and signoff quality, while collaborating with cross-functional teams and contributing to flow improvements.
nResponsibilities
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- Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocksn
- Drive timing closure across multi-mode, multi-corner scenariosn
- Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoffn
- Conduct power integrity analysis (IR drop, EM) and support PDN optimizationn
- Support DFT implementation and ensure proper test structure integrationn
- Analyze and debug timing, congestion, power, and signal integrity issuesn




- Execute ECOs and support tape-out readiness under tight schedulesn
- Develop and use automation scripts to improve flow efficiencyn
- Contribute to methodology improvements and standardization effortsn
- Collaborate with team members on implementation strategies, constraints, and floorplansn

nQualification
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- Bachelor's or Master's degree in Electronics / Electrical Engineering or related fieldn
- 2–6 years of hands-on experience in digital physical design of SoCs or ASICsn
- Proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)n
- Solid understanding of:n
- ○ Floorplanning and power planning basicsn
- ○ Placement and routing optimizationn
- ○ Clock tree synthesis (CTS)n
- ○ Static Timing Analysis (STA) and timing closure techniquesn
- ○ Physical verification and reliability checksn
- Exposure to

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