Job DescriptionPrimary purpose of the role
nThe role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation. The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams.
nThis is a hands-on individual contributor role requiring solid expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.
nMajor responsibilities:
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RTL Design & FPGA Implementationn
Clocking, CDC & Reset Architecturen
High-Speed LVDS & Data Capturen
Timing Closure & FPGA Optimisationn
Verification & Validationn
Hardware Bring-Up & Debuggingn
FPGA Configuration & Release Managementn
Cross-Functional Collaborationn
Documentation & Design Governancen

📌 Field Programmable Gate Arrays Engineer Maharashtra
🏢 Metal Power Analytical
📍 Maharashtra