Job Description

Lead Static Timing Analysis (STA) Engineer

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Experience: 6 to 10 years of experience in STA.

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Location :- Bangalore

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Job Summary

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The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.

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Key Responsibilities

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Timing Sign-off and Analysis
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Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.
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Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).
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MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).
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Critical Path Identification:



Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.
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Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.
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Methodology and Flow

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Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.
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Automate repetitive tasks and report generation using scripting languages.
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Generate final timing reports and sign-off collateral for tape-out.
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Education

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Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.
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Technical Skills

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EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.
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📌 Lead Static Timing Analysis Sta Engineer Bengaluru (India)
🏢 leadsoc technologies
📍 India