Job Type: Full time

Lead / Principal Physical Design Engineer (Team Lead) Location: Ahmedabad, India (Sasken Silicon)Function: ASIC Backend / Physical Design Reports to: PD Engineering Manager / Silicon Delivery Head Team: Leads a pod of ~10 junior–to–mid PD engineers (PD, STA, DFT, PV)Engagement context: Advanced-node (Intel 18 A / sub-3nm) backend programs Role Summary We are looking for an experienced Physical Design lead to own the backend implementation of a high-performance digital IP on an advanced process node, from synthesis through tapeout-ready GDS-II. Beyond hands-on technical depth, this person must be able to lead and grow a team of ~10 junior PD engineers — distributing work, reviewing quality, unblocking the team, and driving convergence against tight Qo R and schedule targets. This is a delivery-ownership role: the lead is accountable for floorplan strategy, timing/power/area closure, signoff quality, and on-time tapeout, while mentoring less-experienced engineers to operate at advanced-node standards. Key Responsibilities Technical ownership Own the full RTL-to-GDS physical design flow: synthesis, floorplanning, placement, CTS, routing, and signoff. Define floorplan and power-delivery strategy, including advanced-node considerations such as backside power delivery (Power Via) and gate-all-around / Ribbon FET cell handling where applicable. Drive timing closure across all PVT corners (MMMC, AOCV/POCV), including setup/hold, signal integrity, and complex timing ECOs. Own physical verification closure (DRC/LVS, antenna, PERC), power/EM/IR integrity, and thermal / self-heating (SHE) signoff. Manage memory and macro integration (e.g., large SRAM arrays), congestion management, and high pin-density datapath closure. Set up and validate the PD flow on a new PDK, including tool/flow bring-up and "pipe-clean" trial runs. Team leadership (critical) Lead a pod of ~10 junior PD engineers: assign blocks/tasks,



set technical direction, and balance load dynamically across project phases. Review the team's work — floorplans, timing reports, signoff results — and enforce quality gates before handoff. Mentor and upskill junior engineers on advanced-node methodology, debugging, and tool usage. Run review-gate checkpoints (floorplan signoff, CTS targets, release candidates) and present status, risks, and Qo R to internal and customer stakeholders. Coordinate handoffs with RTL/DV, DFT, and PV/signoff specialists, and drive rapid issue resolution on ECOs and debug requests. Required Qualifications Education: B. E./B. Tech or M. E./M. Tech in Electronics, Electrical, VLSI, or related field. Experience: 10+ years in ASIC physical design, with a strong track record of taping out production silicon. (Adjust per band: ~8+ for Lead, ~12+ for Principal.) Team experience: Demonstrated experience leading/mentoring a team of PD engineers and owning delivery for a block or full chip — not just individual-contributor work. Full-flow depth: Hands-on ownership across synthesis, Pn R, CTS, routing, STA, and physical/electrical signoff. Advanced-node experience: Proven work at 7nm/5nm/3nm or below; Fin FET closure mandatory, gate-all-around / advanced-node exposure a strong plus. Tools: Strong hands-on with the Synopsys + Siemens flow used on this program: Synthesis & Pn R: Synopsys Fusion Compiler (or Design Compiler + ICC2) Timing: Synopsys Prime Time (incl. SI / ECO) Extraction: Synopsys Star RC Formal/LEC:



Synopsys Formality Physical verification: Siemens Calibre (nm DRC, nm LVS, PERC, multi-patterning) DFT: Siemens Tessent (scan, Memory BIST, boundary scan) Power/IR/EM: Ansys Red Hawk-SC (Cadence Innovus/Tempus/Quantus exposure is a plus for flow flexibility.) Methodology: Solid grasp of low-power design (multi-Vt, clock/power gating, multi-voltage domains), CDC handling, DFT integration, and signoff-quality Qo R metrics (WNS/TNS, 0-violation DRC/LVS, EM, thermal). Scripting: TCL and Python (Perl a plus) for flow automation and productivity. Preferred / Nice-to-Have Direct experience on Intel 18 A (Ribbon FET, Power Via / backside power) or another foundry's gate-all-around / backside-power node. Experience on high-throughput DSP / wireless / MIMO datapaths, systolic arrays, or large matrix-compute blocks. Experience working with foundry PDKs at early maturity (PDK 0.9/1.0) and managing flow risk on evolving RTL. Experience operating in a fixed-timeline, milestone/review-gate delivery model with customer-facing checkpoints. Familiarity with HPC compute environments (large-RAM nodes) for advanced-node layouts. What Success Looks Like (First 6–9 Months) Stands up and validates the PD flow on the target PDK and completes a clean trial run. Locks a floorplan and power-grid strategy that clears the first review gate. Brings the pod of ~10 engineers to predictable, reviewable output with consistent quality. Drives the design to a tapeout-ready, 0-violation GDS-II within the agreed schedule. Core Competencies We Screen For Technical depth at advanced nodes and the leadership maturity to run a 10-person team. Ability to break a large backend program into block-level tasks and delegate effectively. Calm, structured problem-solving under schedule pressure. Clear communication of status, risk, and trade-offs to both engineers and stakeholders.

📌 Lead engineer (Gujarat)
🏢 Sasken Technologies
📍 Gujarat