Job DescriptionExperience : 3+ Years
NNotice Period: Immediate to 30 days.
NJob Description:
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- Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus) N
- Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure N
- Work closely with design team to come up with preplacement requirements & timing constraints N
- Work closely with physical design team for floorplan, placement & timing reviews N
- Work closely with cross-functional teams to review standard cell profile, timing models & memory models N

nSkills:
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- Positive understanding of ASIC design flow N
- Hands on experience in synthesis and static timing analysis N
- Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must N

nExperience in Perl, TCL and shell scripting is desirable
N* Excellent interpersonal& analytical skills with ability to work independently
NBachelors or Master's Degree with a strong VLSI Background

📌 Hiring: Synthesis Engineer (Karnataka)
🏢 Mirafra Technologies
📍 Karnataka