Job Description: Candidate must have positive understanding of the System-Verilog, UVM and Test case development. Must have good debugging skills Required experience in Cadence Tool chain (Xcellium) Experience in AMBA protocol (AXI3/4, AHB, APB)Experience in usage of 3rd party VIP is plus Experience in PCIe protocol is plus
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Regards,
Jaya
📌 DV Profiles with PCie and Xcellium (India)
🏢 UST
📍 India
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