We are seeking a Senior IP Design engineer with significant hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.
Key Skills
- Hands-on experience in FPGA RTL design, logic verification, debug and timing closure
- Programming skills (e.g.: C/C++, Perl, TCL or Python)
- Experience in hardware validation and debug is a plus
- Experience in soft IP packaging, example design and testbench development will be an added advantage
Education and General
- BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA system design experience.
- Independent and self-motivated, capable of executing under agile environment and uncertainties
This position requires a successful background and reference checks and satisfactory proof of your right to work in India.
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