15 Sep
|
Avant Garde
|
Bengaluru
15 Sep
Avant Garde
Bengaluru
- Senior ASIC verification role requiring 8-15 years of hands-on block, subsystem and chip-top verification.
- The incumbent will develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG simulations.
- Scripting in Perl, Python or Shell, collaboration with analog and architecture teams, FPGA-based validation, lab bring-up and customer-debug support are also required.
- This is a full time work-from-office role in Bengaluru.
📌 Senior Verification Engineer - ASIC (Bengaluru)
🏢 Avant Garde
📍 Bengaluru