Job DescriptionSenior Memory Layout Engineer

NLocation: Bengaluru

NExperience: 4–10 Years

NRole Overview

nWe are looking for a Senior Memory Layout Engineer with strong hands-on expertise in memory/custom layout for advanced technology nodes, including 2nm, 3nm, and 5nm FinFET processes.

NKey Responsibilities

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- Develop memory macro and custom layouts from floorplan through tapeout.
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- Work on SRAM bitcell, memory arrays, and peripheral circuit layouts.
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- Execute layout optimization for area, density, matching, parasitics, and performance.
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- Implement advanced-nodeFinFET layout techniques and design-rule requirements.
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- Perform and debug DRC, LVS, ERC, PEX and physical verification.
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- Analyze parasitic effects, EM/IR and layout-dependent effects.
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- Collaborate with MemoryDesign, Circuit Design, Physical Verification and Technology teams.
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- Support tapeout, signoff and post-layout correlation.
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nCore Technical Skills

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- 4–10 years of Memory / Custom Layout experience.
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- Strong hands-on experience with 2nm / 3nm / 5nm FinFET technologies.
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- Expertise in SRAM / memory macro layout and advanced-node design rules.
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- Strong knowledge of matching, symmetry, shielding, guard rings and sensitive-net routing.
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- Proficiency in Cadence Virtuoso / Custom Layout.
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- Experience with Calibre/ PVS, DRC, LVS, ERC and PEX.
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- Strong understanding ofparasitic optimization and layout-dependent effects.
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- Advanced-node tapeout experience is highly preferred.
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nIdeal Profile: A hands-on memory layout engineer capable of delivering tapeout-quality SRAM/memory layouts at advanced FinFET nodes, with solid ownership of area, quality, parasitics and physical verification.

📌 Senior Memory Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru