15 Sep
|
Velaura AI
|
Bengaluru
15 Sep
Velaura AI
Bengaluru
We are seeking a highly experienced Physical Verification Engineer – Staff / Sr. Staff to own full-chip physical verification and signoff for advanced SoC/ASIC designs. The candidate will have end-to-end responsibility for physical verification from block-level implementation and verification through full-chip integration and final tape-out.
The role requires solid hands-on expertise in DRC, LVS, ERC, PERC, antenna, ESD and reliability verification, along with the ability to debug and implement physical fixes directly in Cadence Innovus and Synopsys Fusion Compiler.
The candidate will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability and CAD teams to drive signoff closure and achieve first-time-right silicon.
📌 Physical Verification Engineer (Bengaluru)
🏢 Velaura AI
📍 Bengaluru