Position: Memory & Data-Movement / Chiplet Architect (IRT712ST RM 4408)

Position Summary

Develop models and architecture studies for HBM, DDR, CXL memory, and system-level data movement in AI infrastructure.

Work mode : Hybrid

Education : B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical, Computer Engineering, or related discipline.

Key Responsibilities

- Memory / Data-Movement Modelling: Develop functional/ performance models for HBM/DDR/memory subsystems; model memory bandwidth, latency, and access patterns; model DMA and high-volume data movement; analyze buffering, queues, and traffic patterns; evaluate CXLbased memory architectures.
- Multi-Chiplet / Multi-XPU Scalability: Analyze memory scaling with multiple XPUs/chiplets, study aggregate bandwidth requirements, and identify memory bottlenecks in multi-XPU configurations.
- System Performance & Architecture Exploration: Perform memory architecture trade-offs, evaluate bandwidth vs. latency vs. capacity, and correlate memory behavior with AI workload requirements.

Required Technical Skills

- HBM / DDR.
- 7–12+ years of semiconductor/system architecture experience.
- Memory controllers.




- Data movement / DMA.
- SystemC/TLM.
- C++ / Python.
- AI/HPC system architecture.

Preferred Skills

- Chiplet architecture, UCIe, PCIe.
- Cache/coherency.
- HBM2E / HBM3 / HBM3E.
- AI accelerator architecture.

Project Experience : Hands-on memory/data-movement architecture or modelling work on HBM, DDR, or CXL-based memory systems.

Soft Skills

- Strong quantitative reasoning across bandwidth, latency, and capacity trade-offs.
- Ability to correlate memory-subsystem behavior with AI workload requirements for non-memoryspecialist stakeholders.

Valuable to Have

- Direct HBM2E/HBM3/HBM3E architecture or modelling experience.
- Exposure to cache/coherency design in a multi-chiplet system.

Expected Deliverables

- Functional/performance models for HBM/DDR/CXL memory subsystems.
- Memory scaling analysis across multi-XPU/chiplet configurations.
- Memory architecture trade-off studies (bandwidth vs. latency vs. capacity).

Growth Path : Progress into Principal Memory Architect or Memory Subsystem Practice Lead roles.

📌 Memory & Data-Movement / Chiplet ArchitectST RM 4408) (Hyderabad)
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📍 Hyderabad