The role: The candidate will get to work on the verification of complex PLLs that are delivered to various AMD SoCs.
The person: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have solid analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
- Verification of IP features: Test plan creation, verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
- Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
- Reviews, and feedback to design/architecture teams.
Preferred Experience
- Years of experience 15+ Required.
- Expertise in System Verilog,
methodology based testbench architectures such as UVM, and System Verilog assertions (SVA)
- Expertise in code and functional coverage.
- Excellent Problem solving and debugging skills.
- Excellent Communication skills
- Strong digital design knowledge.
- Exposure to UPF based low power RTL verification.
- Prior experience in leading a team is desirable.
- Prior experience in PLL verification and Mixed signal verification methodology is highly desirable.
- Exposure to digital-analog co-simulations (cosims) is desirable.
Academic Credentials
- Bachelors or Masters degree in Electronics engineering/Electrical Engineering
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