Looking for a Design Verification Engineer with 7-10 years of ASIC/SoC verification experience, robust expertise in UVM, Formal Verification, SystemVerilog/Verilog, verification environment development, debugging, and scripting (Python/Perl)

Mandatory Skills

- 7 to 10 years of experience in Design Verification (DV) for ASIC/SoC
- Strong hands-on experience in UVM (Universal Verification Methodology)
- Experience in Formal Verification
- Strong knowledge of Verilog/SystemVerilog or VHDL
- Experience in developing and debugging complex testbenches and verification environments
- Strong understanding of RTL design concepts
- Experience with simulation tools such as: Synopsys VCS,Cadence Incisive/Xcelium,ModelSim,
- Scripting experience in Python or Perl
- Strong debugging and root cause analysis skills

Preferred Skills
- Experience with formal verification tools
- Team leadership or mentoring experience
- ASIC/SoC verification at block and subsystem level
- Code reviews and verification methodology improvements

📌 Design Verification Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru