Develop functional and performance models for the company’s chiplet connectivity and high-speed datamovement infrastructure, including UCIe, PCIe, CXL, and die-to-die interfaces.
Education : B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical, Computer Engineering, or related discipline.
Key Responsibilities
- Connectivity Virtual Modelling: Develop SystemC/TLM models of connectivity components; model transactions, data movement, latency, and bandwidth; develop configurable models for different link configurations; represent software-visible behavior where required.
- AI Scale-Up / Fabric Modelling: Model communication between multiple XPUs/chiplets, develop scalable interconnect/fabric models, and analyze bandwidth, latency, congestion, and utilization to support scale-up architecture exploration.
- Multi-Chiplet / Multi-XPU Scalability: Integrate connectivity models into multi-chiplet configurations and evaluate communication scalability as the number of XPUs/chiplets increases.
Required Technical Skills
- 5–10+ years of relevant SystemC/TLM or connectivity-modelling experience.
- Robust C++ / SystemC / TLM.
- UCIe, PCIe,
and CXL.
- Chiplet architecture and high-speed interconnects.
- Transaction-level modelling and performance modelling.
Project Experience : Hands-on development of SystemC/TLM connectivity or interconnect models (UCIe/PCIe/CXL or dieto-die) used for bandwidth/latency analysis.
Soft Skills
- Strong modelling discipline and attention to protocol-level detail.
- Ability to work closely with the platform architect and performance architect to integrate models cleanly
Good to Have
- Experience modelling scale-up fabrics for multi-XPU AI systems.
- Familiarity with SerDes/UALink for next-generation interconnects.
Expected Deliverables
- SystemC/TLM functional and performance models for UCIe/PCIe/CXL and die-to-die interfaces.
- Scalable interconnect/fabric models integrated into multi-chiplet configurations.
- Bandwidth/latency/congestion analysis reports.
Growth Path
- Progress toward Senior Connectivity Architect or Interconnect/ Fabric Architecture Lead roles.