Job DescriptionAIML Pipeline / Dataflow Design Lead

NLocation: Bangalore, India |Company: LTSCT — L&T; Semiconductor Technologies Limited

NReporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)

NRole Summary

nWe are hiring two AIML Pipeline / Dataflow Design Leads to implement the BFOS-MPE (Broadcast-Fed Output-Stationary Matrix Processing Engine) — the compute heart of xPU. You will own the compute datapath, the broadcast network, PE array control, sparsity engines (SWS), and dual-mode (matrix + GPU) switching. You will also own the LLVM interface to the xPU.

NKey Responsibilities

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- Own micro-architecture and RTL of the BFOS-MPE compute datapath — dual 256×256 PE arrays (65,536 PEs each) operating at 2 GHz.
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- Design the broadcast-fed input network and output-stationary accumulation scheme that define the BFOS dataflow.
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- Implement PE array control, sequencing, and the sparsity engine (SWS) for structured/unstructured sparsity acceleration.
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- Architect dual-mode operation enabling switching between dense matrix (GEMM/convolution) and GPU-style workloads.
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- Drive numerical formatsand precision (FP/BF/INT, mixed precision) and validate functional correctness against reference models.
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- Coordinate and integrate contributions into the dataflow codebase and verification plan.
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- Own performance/utilization modeling, power-efficiency optimization, and PPA closure for the compute engine.
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- Own the ISA/FW routinesfor the optimal utilization of the HW compute structures in the xPU;





as part of the LLVM development.

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nRequired Skills & Experience

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- 10+ years in compute datapath, DSP, GPU, or AI-accelerator micro-architecture and RTL design.
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- Deep understanding of systolic/spatial arrays, matrix-multiply dataflows (output/weight/row-stationary), and broadcast networks.
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- Robust expertise in RTL(SystemVerilog) for high-throughput arithmetic datapaths and control.
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- Solid grounding in numerical formats and arithmetic (FP32/BF16/FP8/INT8), mixed-precision, and rounding/accuracy trade-offs.
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- Experience with sparsity acceleration techniques (structured/unstructured, weight/activation sparsity).
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- Familiarity with deep-learning operators (GEMM, convolution, attention) and how they map to hardware.
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- Ability to build and correlate performance/utilization models against RTL and reference software.
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- Hands-on PPA optimization for large, dense compute blocks.
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- Proficiency in C/C++/Python for modeling and verification support.
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- Proven leadership and experience integrating cross-organization/partner engineering contributions.
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- AI compiler developmentexperience is a definite plus.
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nPreferred Qualifications

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- Direct experienceon a taped-out AI/ML accelerator or tensor/matrix engine.
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- Familiarity with GPU SIMT execution models and matrix+vector dual-mode designs.
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- Exposure to ML compiler/graph mapping (MLIR, TVM) and how software drives the datapath.
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- M.Tech/MS/PhD in EE/ECE/CS or equivalent.
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📌 Aiml Pipeline/ Dataflow Design Lead (Karnataka)
🏢 Lu0026T Semiconductor Technologies
📍 Karnataka