About the Company We are looking for an experienced DFT Lead with strong expertise in Design-for-Test implementation for complex SoC and ASIC designs. The candidate will be responsible for planning, implementing, verifying, and signing off DFT structures across multiple blocks and full-chip designs. The role requires strong technical knowledge of scan architecture, ATPG, memory testing, test compression, boundary scan, and physical-design-aware DFT implementation. The candidate will also provide technical leadership, guide junior engineers, and collaborate with RTL, synthesis, physical design, verification, and product engineering teams.About the Role DFT Lead Location: Bangalore, Chennai ,Malaysia and Japan Experience: 7+ Years and 4+ years Employment Type: Full-Time Role: DFT Lead / Senior DFT Engineer Responsibilities Define and implement the DFT architecture for block-level and full-chip SoC designs. Perform scan insertion, scan stitching, scan compression, and scan reordering.Develop and implement ATPG strategies for stuck-at, transition, path-delay, and other fault models. Implement and verify MBIST, LBIST, IJTAG, JTAG, and boundary-scan architectures. Perform DFT rule checks, debug violations, and ensure design readiness for ATPG. Generate and validate production-quality test patterns.Analyse ATPG coverage and improve fault coverage through test-point insertion and design enhancements. Perform pattern simulation at RTL, gate level, and timing-annotated netlist levels. Debug scan-chain failures, pattern mismatches, X-propagation issues, and coverage gaps. Work closely with physical design teams on scan-chain placement, scan reordering, congestion, timing, and routing issues.Support low-power DFT implementation for designs involving multiple power domains, isolation, retention, and power gating. Perform DFT timing analysis and resolve setup, hold,



and clock-related issues in test mode. Support post-silicon bring-up, silicon debug, yield analysis, and diagnosis of manufacturing test failures.Prepare DFT specifications, implementation guidelines, test-mode documentation, and sign-off reports. Lead technical reviews and ensure adherence to project quality and schedule requirements. Mentor junior engineers and provide technical guidance across the DFT implementation flow. QualificationsB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, Computer Engineering, or a related discipline. Required Skills 7+ years of hands-on experience in DFT implementation for ASIC or SoC designs. Solid expertise in scan insertion, ATPG, scan compression, and test-pattern generation.Hands-on experience with MBIST, LBIST, JTAG, boundary scan, and IJTAG. Strong understanding of stuck-at, transition-delay, path-delay, bridging, and cell-aware fault models. Experience with hierarchical and full-chip DFT implementation. Strong knowledge of DFT rule checking and testability analysis.Experience in debugging ATPG coverage, scan-chain issues, simulation failures, and test-mode timing problems. Good understanding of synthesis, static timing analysis, clock-domain crossing, reset architecture, and physical design. Experience working with low-power designs using UPF or CPF. Strong scripting skills in Tcl, Perl, Python, or Shell.Proficiency in Verilog and SystemVerilog. Experience with gate-level simulation and SDF-annotated pattern simulation. Strong analytical, debugging, communication, and technical leadership skills. Preferred Skills Hands-on experience with one or more of the following tools: Siemens TessentSynopsys DFT Compiler Synopsys TestMAX Cadence Modus Synopsys VCS Cadence Xcelium Siemens Questa Synopsys PrimeTime Equal Opportunity Statement We are committed to diversity and inclusivity.

📌 DFT Lead Engineer, Bengaluru (India)
🏢 Important Group
📍 India