Hi All,

nGreetings from Eximietas Design...!

nEximietas Hiring Senior Director – DFT_Hyderabad_Bengaluru

nLocations:

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- India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
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nSan Jose (Bay Area), USA

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- Eligibility (USA): U.S. Permanent Residents (Green Card holders).
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nExperience: 25+ Years.

nJob Description:

nWe are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether

nyou are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles

nthat will challenge and grow your skills in advanced silicon testing.

nYou will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across

ncomplex IP, subsystem, and SOC designs.

nCore Responsibilities:

n End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

n Scan architecture definition and implementation at RTL and gate level, including EDT and

nOCC.

n Execution of block-level ATPG, DRC analysis, and coverage optimization.

n Handling of pattern simulations, including both timing and non-timing simulations.

n SOC-level integration, including pattern retargeting to subsystem and full-chip levels.

n Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).

n Independent debugging of DFT simulations and netlist-related issues.

n Close collaboration with design, verification, and physical design teams to ensure DFT

nreadiness.

n Ownership of DFT sign-off activities and deliverables.

nKey Responsibilities:

n Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.

n Perform scan insertion, ATPG generation, and pattern validation at block and top levels.





n Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.

n Define and execute DFT strategies aligned with project requirements and schedules.

n Support pre-silicon and post-silicon test requirements.

n Serve as the DFT point of contact for assigned projects, responsible for verification and test

nreadiness sign-off.

nTechnical Requirements:

nMust-Have Skills:

n Solid experience in netlist handling and ATPG simulations.

n Proven expertise in block-level and SOC-level pattern retargeting and debugging.

n In-depth understanding of ICL and PDL standards.

n Hands-on experience with at least one major DFT tool suite:

no Siemens Tessent

no Synopsys TestMAX / TetraMAX

no Cadence Modus

nPreferred & Advanced Skills:

n Experience with Streaming Scan Network (SSN).

n Knowledge of Analog and Mixed-Signal DFT methodologies.

n Proficiency with SpyGlass for DFT linting and early-stage analysis.

n Exposure to RTL-level DFT insertion and validation.

n Strong scripting skills (TCL, Python, Perl) for automation.

nWhat We Offer:

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- Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
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- Collaborative and inclusive work environment.
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- Competitive compensation and benefits package.
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- Professional growth and development opportunities.
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nIf this opportunity interests you—or if you know someone suitable—please send your updated resume to: [email protected].

nContact: +91 (phone hidden).

nReferrals are highly appreciated.

nBest regards,

nMaruthy Prasaad

nAssociate VLSI Manager - Talent Acquisition | Visakhapatnam

nEximietas Design

[email protected]

n+91 (phone hidden).

📌 Senior Director - DFT_Hyderabad (Hyderabad)
🏢 Eximietas Design
📍 Hyderabad