Job Title: Lead DFT Engineer

Experience: 7+ Years

Location: Bangalore

Employment Type: Full-time

Industry: Semiconductors / ASIC / So C Design

Job Summary

We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex So C/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Key Responsibilities

Define and drive DFT strategy and architecture for multiple ASIC/So C projects. Lead implementation and verification of DFT features like: Scan insertion and compression (e.g., EDT) ATPG pattern generation and fault grading MBIST and Logic BIST insertion and validation Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687) Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up. Collaborate with RTL, STA, PD, and test engineering teams for seamless integration. Perform pattern generation, fault simulation, and debug test coverage gaps. Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery. Support silicon bring-up, test vector validation on ATE, and yield optimization. Mentor and guide junior DFT engineers; conduct design reviews and training sessions. Develop and maintain DFT automation scripts and infrastructure.





Required Skills and Experience

B. E./B. Tech or M. E./M. Tech in Electronics, Electrical, or VLSI Design. 7+ years of experience in DFT for complex ASIC or So C designs. Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. Hands-on experience with DFT tools such as: Synopsys: DFT Compiler, Tetra MAX, Test MAX Siemens EDA: Tessent Scan Pro, MBIST, IJTAG Cadence/others: Modus, Encounter Test Solid knowledge of RTL design, STA, and synthesis flows. Proficient in scripting languages (Python, Perl, Tcl) for flow automation. Deep understanding of silicon test challenges and test coverage improvement. Strong leadership, team collaboration, and communication skills.

Preferred

Qualifications

Experience with hierarchical DFT and low-power DFT methodologies (UPF). Exposure to post-silicon validation and failure analysis. Familiarity with safety-critical designs (ISO 26262) and functional safety. Experience working in advanced nodes (e.g., 7nm, 5nm, Fin FET). Why Join Us?

Lead DFT for high-performance, next-gen So Cs and ASICs. Collaborate with top-tier engineers and global semiconductor leaders. Competitive salary, leadership exposure, and fast-track growth opportunities. Interested can share CV to sharmila.b@

📌 Lead Dft Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru