Job Description

About the Company

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We are looking for an experienced DFT Lead with strong expertise in Design-for-Test implementation for complex SoC and ASIC designs. The candidate will be responsible for planning, implementing, verifying, and signing off DFT structures across multiple blocks and full-chip designs. The role requires strong technical knowledge of scan architecture, ATPG, memory testing, test compression, boundary scan, and physical-design-aware DFT implementation. The candidate will also provide technical leadership, guide junior engineers, and collaborate with RTL, synthesis, physical design, verification, and product engineering teams.

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About the Role

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DFT Lead

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Location: Bangalore, Chennai ,Malaysia and Japan

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Experience: 7+ Years and 4+ years

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Employment Type: Full time

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Role: DFT Lead / Senior DFT Engineer

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Responsibilities

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- Define and implement the DFT architecture for block-level and full-chip SoC designs.
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- Perform scan insertion, scan stitching, scan compression, and scan reordering.
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- Develop and implement ATPG strategies for stuck-at, transition, path-delay, and other fault models.
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- Implement and verify MBIST, LBIST, IJTAG, JTAG, and boundary-scan architectures.
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- Perform DFT rule checks, debug violations, and ensure design readiness for ATPG.
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- Generate and validate production-quality test patterns.
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- Analyse ATPG coverage and improve fault coverage through test-point insertion and design enhancements.
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- Perform pattern simulation at RTL, gate level, and timing-annotated netlist levels.
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- Debug scan-chain failures, pattern mismatches, X-propagation issues, and coverage gaps.
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- Work closely with physical design teams on scan-chain placement, scan reordering, congestion, timing, and routing issues.
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- Support low-power DFT implementation for designs involving multiple power domains, isolation, retention, and power gating.
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- Perform DFT timing analysis and resolve setup, hold,



and clock-related issues in test mode.
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- Support post-silicon bring-up, silicon debug, yield analysis, and diagnosis of manufacturing test failures.
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- Prepare DFT specifications, implementation guidelines, test-mode documentation, and sign-off reports.
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- Lead technical reviews and ensure adherence to project quality and schedule requirements.
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- Mentor junior engineers and provide technical guidance across the DFT implementation flow.
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Qualifications

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- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, Computer Engineering, or a related discipline.
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Required Skills

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- 7+ years of hands-on experience in DFT implementation for ASIC or SoC designs.
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- Strong expertise in scan insertion, ATPG, scan compression, and test-pattern generation.
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- Hands-on experience with MBIST, LBIST, JTAG, boundary scan, and IJTAG.
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- Strong understanding of stuck-at, transition-delay, path-delay, bridging, and cell-aware fault models.
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- Experience with hierarchical and full-chip DFT implementation.
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- Strong knowledge of DFT rule checking and testability analysis.
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- Experience in debugging ATPG coverage, scan-chain issues, simulation failures, and test-mode timing problems.
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- Good understanding of synthesis, static timing analysis, clock-domain crossing, reset architecture, and physical design.
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- Experience working with low-power designs using UPF or CPF.
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- Strong scripting skills in Tcl, Perl, Python, or Shell.
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- Proficiency in Verilog and SystemVerilog.
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- Experience with gate-level simulation and SDF-annotated pattern simulation.
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- Strong analytical, debugging, communication, and technical leadership skills.
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Preferred Skills

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- Hands-on experience with one or more of the following tools:
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- Siemens Tessent
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- Synopsys DFT Compiler
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- Synopsys TestMAX
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- Cadence Modus
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- Synopsys VCS
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- Cadence Xcelium
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- Siemens Questa
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- Synopsys PrimeTime
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Equal Opportunity Statement

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We are committed to diversity and inclusivity.

📌 DFT Lead Engineer (Bengaluru)
🏢 XQwave(Formerly Obsidian Solutions
📍 Bengaluru