Kindly note that working from India, Bangalore office is non-negotiable.
- Positive knowledge in Cadence Palladium flows
- Post Silicon debug experience
- Reproduction of Si issues on palladium
- Running/ porting SW tests on palladium
- Peripheral (uart, spi, i2c etc) protocol and debug knowledge
- Writing C test cases
- Writing tests cases in post Si bench (mostly Py controlled)