Job Description

Our Client is Leading SOC developer it's headquaters is in Korea,

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CTC: As per market standards

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Exp: 12+ yrs

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Location: Bangalore

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Key Responsibilities

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SoC DFT Architecture & Leadership

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- Own SoC-level DFT architecture and strategy for custom and platform-based SoCs.
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- Define and drive DFT implementation plans across multiple concurrent SoC programs.
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- Act as the technical authority and signoff owner for all DFT-related decisions and deliverables.
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Execution & Technical Ownership

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- Lead DFT RTL integration, scan insertion, and test architecture implementation.
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- Own and drive:
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- Scan, Compression, and ATPG strategy
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- MBIST, BISR, and redundancy implementation
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- JTAG / TAP, Boundary Scan, and debug infrastructure
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- Ensure DFT readiness across functional, scan, and low-power modes.
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- Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and implementation.
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- Drive ATPG pattern generation, simulation, and debug to ensure high test coverage and quality.
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Cross-Functional & Manufacturing Interface

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- Work closely with physical design teams to ensure scan and test logic closure with minimal PPA impact.
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- Interface with manufacturing, ATE, and OSAT teams on test requirements, vector delivery, and silicon bring-up.
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- Support post-silicon debug, yield ramp, and test optimization.
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- Represent Semifive in customer-facing technical discussions related to DFT strategy and signoff.
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Methodology & Team Development

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- Define and standardize DFT methodologies, flows, and checklists across Semifive programs.
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- Drive automation, scripting, and reuse to improve DFT efficiency and predictability.
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- Mentor and develop DFT engineers and leads, building deep technical and execution capability.
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- Review and approve DFT signoff reports and tapeout readiness criteria.
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Qualifications

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- B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
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- 12+ years of experience in DFT architecture and implementation for complex SoCs.
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- Proven track record of leading DFT implementation and signoff on multiple custom SoC tapeouts.
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- Solid expertise in:
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- Scan, Compression, and ATPG methodologies
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- MBIST, BISR, and memory repair schemes
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- JTAG / TAP and Boundary Scan
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- DFT RTL integration and pattern simulation
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- Hands-on experience with industry-standard DFT tools, such as:
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- Siemens Tessent
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- Synopsys DFTMAX / TestMAX
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- SpyGlass DFT (or equivalent)
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- Strong understanding of:
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- Low-power DFT challenges (UPF/CPF)
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- Scan and test-mode timing closure
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- Physical implementation constraints for DFT
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- Experience working with manufacturing, ATE, and post-silicon validation teams.
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- Excellent problem-solving, communication, and leadership skills.
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📌 Lead DFT (Bengaluru)
🏢 M/s Angel and Genie
📍 Bengaluru