Job Description

Job Title: Lead DFT Engineer

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Experience: 7+ Years

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Location: Bangalore

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Employment Type: Full-time

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Industry: Semiconductors / ASIC / SoC Design

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Job Summary:

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We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

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Key Responsibilities:

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- Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
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- Lead implementation and verification of DFT features like:
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- Scan insertion and compression (e.g., EDT)
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- ATPG pattern generation and fault grading
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- MBIST and Logic BIST insertion and validation
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- Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)
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- Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.
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- Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
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- Perform pattern generation, fault simulation, and debug test coverage gaps.
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- Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
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- Support silicon bring-up, test vector validation on ATE, and yield optimization.
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- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
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- Develop and maintain DFT automation scripts and infrastructure.
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Required Skills and Experience:

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- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
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- 7+ years of experience in DFT for complex ASIC or SoC designs.
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- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
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- Hands-on experience with DFT tools such as:
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- Synopsys: DFT Compiler, TetraMAX, TestMAX
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- Siemens EDA: Tessent ScanPro, MBIST, IJTAG
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- Cadence/others: Modus, Encounter Test
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- Strong knowledge of RTL design, STA, and synthesis flows.
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- Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
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- Deep understanding of silicon test challenges and test coverage improvement.
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- Robust leadership, team collaboration, and communication skills.
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Preferred Qualifications:

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- Experience with hierarchical DFT and low-power DFT methodologies (UPF).
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- Exposure to post-silicon validation and failure analysis.
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- Familiarity with safety-critical designs (ISO 26262) and functional safety.
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- Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).
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Why Join Us?

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- Lead DFT for high-performance, next-gen SoCs and ASICs.
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- Collaborate with top-tier engineers and global semiconductor leaders.
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- Competitive salary, leadership exposure, and fast-track growth opportunities.
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Interested can share CV to [email protected]

📌 Lead DFT Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru