Job Title: DFT / Design for Test Engineer (Lead / Principal / Architect) Experience: 3 to 18 Years Location: Bangalore, India (Onsite) Notice Period: Immediate to 90 Days ( Candidates currently serving notice period are highly preferred ) About the Role We are looking for deeply passionate, technically rigorous DFT Engineers across multiple experience levels to join our elite engineering group in Bangalore. Whether you are a rising star with 3 years of execution experience or an industry veteran/architect with up to 18 years of experience, we want individuals who don't just execute scripts, but possess a deep architectural understanding of the why behind test methodologies. This is a long-term career chance for professionals who are genuinely driven to learn, grow, and establish themselves among the top-tier DFT experts in the Indian semiconductor market. Key Responsibilities Architect, design, and implement DFT strategies for complex, high-performance SoCs and AI accelerators. Take complete ownership of tool flows, scripting, and debug constraints for assigned DFT domains.



Collaborate closely with RTL design, synthesis, and post-silicon validation teams to ensure seamlessly integrated test structures. For Senior/Lead roles: Mentor junior engineers, drive DFT architecture definition, and lead chip-level test closure. Required Technical Expertise (Any one or multiple techniques) We are looking for solid, fundamental mastery in any one or a combination of the following techniques and flows: Scan & ATPG: Classic Scan insertion, Compression methodologies, and complex ATPG (Stuck-at, Transition, At-Speed, Cell-Aware). Memory BIST (MBIST): Industry-standard MBIST insertion, repair algorithms, and integration. Logic BIST (LBIST): In-system test architectures, especially crucial for automotive or high-reliability chips. Boundary Scan (BSCAN): Classic IEEE 1149.1 JTAG architecture, implementation, and board-level test support. IJTAG: Deep understanding of IEEE 1687 infr

📌 DFT Engineer (India)
🏢 ACL Digital
📍 India