16 Sep
|
ACL Digital
|
Karnataka
16 Sep
ACL Digital
Karnataka
Role Title: Lead Memory Layout Design Engineer Location: Bangalore and Hyderabad Employment Type: Full time Experience Level: 8years to 20 Years Seniority Level: Mid-Senior / Lead About the Role We are seeking an experienced Lead Memory Layout Design Engineer to drive physical layout execution, floorplanning, and optimization for high-performance memory architectures (SRAM, Register Files, CAM, Compiler Memories, or High-Bandwidth Memory). In this technical leadership role, you will lead a team of layout engineers, collaborate closely with circuit design and SOC integration teams, and ensure high-yield, high-density physical deliverables on cutting-edge advanced nodes (7nm, 5nm, 3nm, and below). Key Responsibilities Technical Leadership: Lead, mentor, and review the work of memory layout design engineers while establishing layout guidelines, methodology improvements, and quality control flows. Floorplanning & Architecture: Execute cell-level, block-level, and array-level floorplanning, optimizing for area, power, performance, and pitch alignment in custom memory architectures.
Physical Verification: Drive complete physical verification closures, including DRC, LVS, ERC, Antenna, and EM/IR (Electro-Migration / IR Drop) analysis across advanced process nodes. Cross-Functional Collaboration: Partner with circuit design, CAD, and SOC integration teams to align on timing, power requirements, and cell-pitch constraints. Project Execution: Manage delivery schedules, layout floorplans, and milestones for memory compilers or custom memory macros from concept to tape-out. Qualifications & Skills Education: Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field. Experience: 7 years of hands-on memory layout design experience with at least 2 years in a technical lead role. Advanced Node Expertise: Deep understanding of layout challenges in sub-7nm process nodes (FinFET / GAA / N3 / N2). EDA Tool Proficiency: Hands-on mastery of Cadence Vir
📌 Lead Memory Layout Engineers (Karnataka)
🏢 ACL Digital
📍 Karnataka