Job Description
We're Hiring | Lead ASIC PD / EMIR Engineer
nAre you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.
nRequired Experience
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- 8+ years of overall VLSI/Physical Design experience is preferred.n
- 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.n
- Strong expertise with industry-standard EMIR analysis and sign-off methodologies.n
- Excellent debugging, analytical, and cross-functional collaboration skills.n

nKey Responsibilities
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- Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.n
- Drive EMIR closure by identifying root causes of power integrity and electromigration violations.n
- Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.n
- Collaborate closely with the Physical Design (PD) team to drive effective IR/EM closure across the chip.n
- Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.n
- Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.n

📌 Lead ASIC PD (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru