16 Sep
|
L&T Semiconductor Technologies
|
Bengaluru
16 Sep
L&T Semiconductor Technologies
Bengaluru
DTMA & Memory Controller Design Lead
Location: Bangalore, India |Company: LTSCT — L& T Semiconductor Technologies Limited
Reporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)
Role Summary
The DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps x PU's compute engine saturated.
Key Responsibilities
Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays. Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth. Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate). Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow. Architect the 512-bank,
8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic. Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency. Define Qo S and flow-control interfaces to the No C and compute engine to prevent stalls and starvation. Drive verification, performance modeling, and bandwidth/latency closure across realistic AI workload traffic. Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs. Required Skills & Experience
10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth So Cs. Deep expertise with DRAM/HBM controller architecture, scheduling, and timing (HBM2 E/HBM3/HBM3 E; HBM4e a robust plus). Strong RTL (System Verilog) design skills for DMA engines, arbiters, and memory schedulers. Solid understanding of multi-bank SRAM architectures, banking/interleaving, and
📌 Dtma & Memory Controller Design Lead (Bengaluru)
🏢 L&T Semiconductor Technologies
📍 Bengaluru