Immediate joiners only

JOB DESCRIPTION

Location - Noida, Bangalore & Hyderabad

Top 5 Required Skills/Mandatory skills
SystemVerilog/UVM testbenches
Functional Verification Experience
Hands on experience in SOC level test bench and test plan development.
Knowledge of Amba Protocols
Clearcase Repository/GVIM/Linux Commands

Required Education: BTech/Mtech with Min. 2-8yrs of Exp.

Key Words:

Advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development, Power-Aware verification

Roles & Responsibilities:

Required exp of 2 to 8 years
Build and maintain UVM/SystemVerilog-based testbenches.
Functional Verification
Write directed and constrained-random test cases.
Use assertions and functional coverage to validate design behavior.




Debug simulation failures and root-cause issues in RTL or testbench.
Power Aware Verification
Coverage and Assertion Closure

Job Description:

Candidate will be responsible for verification plan definition, DV workplace development in SV/UVM, SV/C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and Performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support.

📌 Senior Design Verification Engineer Noida (India)
🏢 Tecquire Solutions
📍 India