Design Verification (DV) Engineer 5+ Years

Key Roles & Responsibilities:
Develop and execute Design Verification plans for complex SoC/IP designs.
Create and maintain SystemVerilog/UVM-based verification settings.
Develop testbenches, test scenarios, test cases and functional coverage.
Perform block, subsystem and SoC-level verification.
Debug simulation failures using tools such as VCS, Xcelium/Questa and Verdi.
Develop and debug SystemVerilog/UVM sequences, drivers, monitors, scoreboards and assertions.
Work with protocols such as AMBA AXI/AHB, PCIe, USB, DDR, Ethernet, UCIe or similar.
Perform functional, regression, coverage and corner-case testing.
Analyze coverage and drive coverage closure.
Identify, debug, track and resolve design/verification issues in collaboration with RTL and architecture teams.
Develop SVA assertions and contribute to formal/low-power verification where applicable.
Participate in verification planning, reviews, sign-off and project milestones.
Mentor junior engineers and contribute to improving verification methodologies and automation.

Required Experience: 5+ years in Design Verification
Locations: Bangalore | Noida | Pune | Ahmedabad | Hyderabad

📌 Soc Verification Engineer Noida (India)
🏢 Einfochips
📍 India