Key Responsibilities
Perform end-to-end RTL-to-GDSII physical design implementation.
Handle floorplanning, power planning, placement, CTS, routing, and timing closure.
Perform Static Timing Analysis (STA) including setup/hold analysis across various PVT corners.
Analyze and resolve timing, congestion, signal integrity, crosstalk, and power-related issues.
Perform ECOs and optimize designs for Power, Performance, and Area (PPA).
Conduct physical verification activities including DRC and LVS.
Analyze IR Drop and Electromigration issues and support design optimization.
Work with UPF for power-intent implementation and verification.
Develop and maintain automation scripts using Tcl, Python, or Perl.
Collaborate with RTL, STA, DFT, and verification teams to resolve implementation issues.
Work in an Agile engineering setting and contribute to design methodologies and flow improvements.