Job Description

We're Hiring | Memory Layout Engineers

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We're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.

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Experience: 4+ Years

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Location: Bangalore

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Key Responsibilities:

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Design memory layouts for various building blocks, including:
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Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
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Integrate top-level memory layouts.
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Perform physical verification using DRC and LVS.
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Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
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Analyze layouts for power integrity and signal integrity.
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Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.
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Required Skills:

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Robust hands-on experience in Memory Layout for advanced technology nodes.

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Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).

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Solid understanding of physical verification, layout methodologies, and semiconductor design flows.

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Scripting knowledge is an added advantage.

📌 Memory Layout Engineer Bengaluru
🏢 SmartSoC Solutions
📍 Bengaluru