Job Description
ACL Digital is hiring an RTL Design Engineer (2-4 years experience) in Hyderabad with a notice period of 0-30 days!
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Key Responsibilities & Skills:
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Core RTL Development: Experience in Verilog HDL for RTL design, microarchitecture specification writing, linting, simulation, and SoC architecture comprehension.
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Timing & Implementation: Solid background in Static Timing Analysis (STA), SDC timing constraints, and working with synthesis/backend teams for physical implementation.
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Tools & Scripting: Proficiency in FPGA/ASIC software toolchains (Vivado/Quartus) and scripting languages (TCL, Python, or Perl).
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Interested candidates can send their resumes directly to
[email protected] .
📌 Senior RTL - FPGA Engineers (Hyderabad)
🏢 ACL Digital
📍 Hyderabad