16 Sep
|
L&T Semiconductor Technologies
|
Vasanthanagar
16 Sep
L&T Semiconductor Technologies
Vasanthanagar
Job DescriptionDTMA & Memory Controller Design Lead
nLocation: Bangalore, India |Company: LTSCT — L&T; Semiconductor Technologies Limited
nReporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)
nRole Summary
nThe DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps xPU's compute engine saturated.
nKey Responsibilities
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- Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays.n
- Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth.n
- Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate).n
- Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow.n
- Architect the 512-bank, 8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic.n
- Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency.n
- Define QoS and flow-control interfaces to the NoC and compute engine to prevent stalls and starvation.n
- Drive verification, performance modeling, and bandwidth/latency closure across realistic AI workload traffic.n
- Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs.n
nRequired Skills & Experience
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- 10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth SoCs.n
- Deep expertise with DRAM/HBM controller architecture, scheduling, and timing (HBM2E/HBM3/HBM3E; HBM4e a strong plus).n
- Robust RTL (SystemVerilog) design skills for DMA engines, arbiters, and memory schedulers.n
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📌 DTMA & Memory Controller Design Lead (Vasanthanagar)
🏢 L&T Semiconductor Technologies
📍 Vasanthanagar