Job DescriptionWe're Hiring Senior RTL (ASIC) Engineers at ACL Digital
nOpen Requirement:
n
- n
- Experience: 6+ years in RTL Design.n
- Availability: We are looking for candidates who can join us on a short notice period.n

nAre you an expert in ASIC front-end design with a passion for building complex SoCs? ACL Digital is expanding its VLSI design team, and we are looking for high-caliber RTL (ASIC) Engineers to join our team.
nWho we are looking for:
nWe are seeking experienced professionals (6+ years) who have a strong foundation in the complete ASIC design flow and can hit the ground running on our current project pipeline.
nCore Responsibilities & Technical Skills:
n
- n
- Design & Coding: Strong expertise in RTL coding using Verilog/SystemVerilog and micro-architecture development.n
- Static Verification: Deep hands-on experience with Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis.n
- Tools:



Proficient in tools such as Synopsys SpyGlass, Questa, or similar static verification platforms.n
- ASIC Flow: Knowledge of synthesis, Logical Equivalence Checking (LEC), and full-chip integration.n
- Protocols: Experience with standard protocols (AMBA AXI/AHB/APB) is highly desirable.n

nWhy Join ACL Digital?
nBe part of a high-growth setting working on advanced node (3nm/5nm) semiconductor projects alongside industry leaders. We value technical depth, ownership, and innovative problem-solving.
nHow to Apply:
nInterested candidates, please share your updated resume at or reach out via DM for more details.
n#Hiring #VLSIJobs #RTLDesign #ASIC #SemiconductorJobs #ACLDigital #DFT #TechCareers #ImmediateJoiners #ASICDesign

📌 Senior RTL Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar